Although printed circuit boards with 6 to 20 (or more) layers have been the focus of most EMI/EMC research, boards with 1 to 4 layers are very common and present significant EMC challenges. (The Missouri S&T EMC Laboratory has worked with low-cost, single-layer boards operating at speeds in excess of 100 MHz.) The goal of this project is to explore and model EMC and Signal Integrity issues with low-cost (1 to 4 layer) boards. Results obtained so far demonstrate the need to revise existing design guidelines and strategies for these boards.