The Missouri S&T EMC Laboratory has studied the problem of effective power bus design and modeling extensively over the past 10 years. Work in this area falls primarily into 4 categories:
The goal of this work is to understand and model the contribution that radiation directly from a printed circuit board power bus has on the radiated emissions from a typical product. Significant progress was made on this project recently, resulting in an expert system algorithm for power bus noise estimation. This work is continuing with an investigation of novel power bus designs that may further reduce radiated emissions associated with the power bus.
Noise on one power bus often couples to another power bus and can result in functional problems and/or radiated emissions. Recently, research at Missouri S&T showed that many power bus isolation schemes commonly used are ineffective. New guidelines were developed for isolating power planes using power islands.
The goal of this project is to develop a comprehensive strategy for providing sufficient power bus decoupling on printed circuit boards at the lowest cost. Is it better to locate power and ground on adjacent layers to take advantage of the interplane capacitance? Or, is it better to locate power and ground planes several layers apart to take advantage of the mutual inductance between traces as they pass between the planes? The answer to these questions depends on the specific application and the design goals. Recently, several boards designed specifically for this project were measured in the Missouri S&T EMC Laboratory. These models were used to evaluate models for selecting the best decoupling strategy for a given application. Although many of the most difficult questions were answered, printed circuit board and component technologies are continuing to evolve ensuring that this will continue to be an active area of research at Missouri S&T.
The Missouri S&T EMC Consortium worked with another consortium of companies directed by the National Center for Manufacturing Sciences to evaluate and model low-cost materials used to substantially increase the interplane capacitance of printed circuit boards. With sufficiently high values of interplane capacitance, the number of surface mount decoupling capacitors on a typical printed circuit board can be significantly reduced. Embedded capacitance materials have other properties that make them much more effective for high-frequency decoupling than discrete components. Missouri S&T developed models that were used to formulate design guidelines for the use of embedded capacitance in high-speed printed circuit boards. Measurements of special test boards were used to validate these models and demonstrate the effectiveness (or ineffectiveness) of embedded capacitance in various applications. We are continuing to study possible new applications of embedded capacitance.